Exemplary embodiments relate to the program method of a semiconductor memory device and, more particularly, to a program method for minimizing interference between neighboring memory cells.
A semiconductor memory device includes a memory cell array for storing data. The memory cell array includes memory cell blocks each including a plurality of memory cells.
There are various methods of programming the memory cells. As an example, an incremental step pulse program (ISPP) method of supplying program voltages, gradually rising, to word lines in order to prevent the widening of a threshold voltage distribution has been used. The ISPP method is described below with reference to the drawings.
FIG. 1 is a circuit diagram showing a part of a memory cell block shown to illustrate a conventional program method.
Referring to FIG. 1, the memory cell block includes a plurality of strings ST. Each of the strings includes a drain select transistor DST, a plurality of memory cells F0 to Fn, and a source select transistor SST which are coupled in series. The drain of the drain select transistor DST is coupled to a bit line BL, and the source of the source select transistor SST is coupled to a common source line CSL. The plurality of memory cells F0 to Fn are coupled in series between the drain select transistor DST and the source select transistor SST. The gates of the drain select transistors DST included in different strings are interconnected to form a drain select line DSL. The gates of the memory cells F0 to Fn included in different strings are interconnected to a plurality of word lines WL0 to WLn. The gates of the source select transistors SST included in different strings are interconnected to a source select line SSL.
A program operation is performed on a page by page basis. Here, the page refers to a group of memory cells coupled to the same word line. When the program operation is started, bit lines BL coupled to memory cells to be programmed are discharged, and the remaining bit lines are precharged. A program voltage is supplied to a word line coupled to a selected page PG, and a program pass voltage is supplied to the remaining word lines. Next, when the drain select transistors DST are turned on, the memory cells to be programmed among the memory cells included in the selected page are programmed according to voltages of the bit lines BL.
In the ISPP method, after selected memory cells are programmed by supplying a program voltage to a selected word line, a verify operation for verifying whether the threshold voltages of the selected memory cells have reached a target level is performed. If there are memory cells having the threshold voltages that have not reached the target level as a result of the verify operation, the program voltage is increased by a step voltage, and the selected memory cells are programmed by increasing the program voltage to the selected word line. Likewise, the program operation is performed while gradually increasing the program voltage until the threshold voltages of all of the selected memory cells reach the target level.
After the program operation for the selected page is completed, a next page is selected and the program operation for the next page is performed. Meanwhile, when the program operation for the selected page is performed, the memory cells, included in an adjacent page, may be subjected to interference. In other words, the threshold voltages of memory cells adjacent to selected memory cells may rise because of interference generated by a high program voltage supplied to a selected word line when the program operation for a selected page is performed. The influence of interference is greater in a multi-level cell (MLC), programmed in various levels, than in a single level cell (SLC).
The influence of interference is described in detail with reference to the following drawing.
FIG. 2 is a graph illustrating threshold voltage distributions shown to illustrate features of a conventional program method.
For example, an MLC that may be programmed with three program states according to the level of a threshold voltage is described below with reference to FIG. 2. In FIG. 2, a threshold voltage graph 10 indicated by a dotted line denotes a threshold voltage distribution before the influence of interference, and a threshold voltage graph 20 indicated by a solid line denotes a threshold voltage distribution after the influence of interference. A margin for distinguishing the states from each other exists between the different threshold voltage distributions 10 and 30. In a read operation, data stored in memory cells to be read can be read by using a read voltage R1, R2, or R3 corresponding to each of the margin section.
For example, if interference is not generated (10), when data stored in selected memory cells are read by using the read level R1, the selected memory cells are read as having been programmed. When the data stored in the selected memory cells are read by using the read level R2, the selected memory cells are read as not having been programmed. Consequently, the threshold voltages of the selected memory cells are determined to be distributed between the read level R1 and the read level R2, and thus the data of the selected memory cells is read as data that is within a corresponding margin.
If the threshold voltages of programmed memory cells become higher than the read level R2 due to interference, when the data of selected memory cells is read by using the read level R2, the selected memory cells with the threshold voltage distribution 10 are changed to have the threshold voltage distribution 20, and thus data different from data before interference is generated may be read.
Furthermore, the interference phenomenon may also vary according an interval between neighboring memory cells.
FIG. 3 is a graph illustrating interference due to an interval between memory cells.
In the graph of FIG. 3, the X axis indicates an interval between gates (that is, an interval between memory cells), and the Y axis indicates the coupling ratio due to interference. From the graph, it can be seen that the influence of interference is greater in a silicon nitride layer than in a silicon oxide under the same interval condition. It can also be seen that the coupling ratio due to interference under the same material condition gradually increases in response to a reduction in the interval and the interference sharply increases at intervals smaller than the interval of 40 nm. It can also be seen that the height of the floating gate of the memory cell is proportional to the interference.
As described above, there are several factors to influence interference. If interference is generated, the level of reliability of a program operation and a read operation is degraded.